There is a bright application future for the semiconductor carbon nanotube (s-CNT) based nano-electronics, which is predicted to be the alternative to silicon based microelectronic integrated circuit technology. According to ten-year research, it is found that s-CNT based nano-electronic devices, especially FET, are superior to silicon based MOSFET on many key device metrics, such as power consumption, speed and integrated density, etc. Additionally, ohmic contact is achieved for hole between palladium and s-CNT, and high performance p-type CNTFET is fabricated A. Javey, J. Guo, Q. Wang, M. Lundstrom, H. Dai, Nature, 424, 654(2003) Besides, scandium is used as electrode to form ohmic contact with s-CNT for electron and fabricate high-performing n-type CNTFET Zhang, Z. Y.; Liang, X. L.; Wang, S.; Yao, K.; Hu, Y. F.; Zhu, Y. Z.; Chen, Q.; Zhou, W. W.; Li, Y.; Yao, Y. G.; Zhang, J.; Peng, L. M. Nano Lett., 7, 3603 (2007) The fabrication process for CNTFET based integrated circuit is very simple related to silicon based CMOS technology mainly due to doping-free and no requirement of high temperature process. Then the cost for CNTFET integrated circuit will be greatly reduced, while the cost is considered to be one of the most important obstacles to the further development of silicon based CMOS technology.
Channel length is one of the vital parameters for FET transistor. In silicon based CMOS technology, speed of devices and integration density of circuit is continuously improved due to the reduction of channel length. The situation is same for CNTFET. To improve devices' speed and density, we have to reduce the channel length, which is defined to be the distance between source-electrode and drain-electrode. As the size of the device becomes smaller and smaller there is a need for a more precise and reliable way to fabricate MOS FETs. The gate-electrode must be posited just between source-electrode and drain-electrode, and cover the channel at the utmost. In this way, the gate can control the channel most efficiently. However, it is necessary to prevent the overlap between gate and source or drain to eliminate large parasitic capacitance and degradation the speed of the transistors. This requirement for alignment between gate and source/drain cannot be achieved only through lithography alignment. So, it is essential to adopt a self-aligned gate structure. In the state-of-the-art silicon based CMOS technology, the use of self-aligned gates is one of the many innovations that has enabled computing power to increase steadily over the last 40 years. A self-aligned structure is therefore necessary for massive fabricating of high performance CNT FETs and for the construction of CNT based CMOS integrated circuits.
One kind of self-aligned structure for CNTFET was developed by professor Dai H J's group from Stanford University Javey, A.; Guo, J.; Farmer, D. B.; Wang, Q.; Wang, D. W.; Gordon, R. G.; Lundstrom, M.; Dai, H. J. Nano Lett., 4, 447 (2004) Hafnium oxide is used as the gate dielectric layer grown by ALD, and aluminum is adopted as the gate electrode. To separate the gate electrode from source and drain electrodes, the aluminum gate electrode is baked in air so that a thin Al2O3 layer was formed at the sidewall. However, there are obvious shortcomings in this method. Firstly, source and drain electrodes should be so thin (typically less than 10 nanometers) that the contact resistance between source/drain electrodes and the channel is consequently very large. More importantly, only these metals that can be oxidized to compact oxide layer can be chosen as the gate electrode. That is, only some low work function metals are suitable. Actually, this limits us to adjust the threshold voltage, which is also an important parameter of FET especially in integrated circuit. Because CNTFETs are doping-free, their threshold voltages cannot be adjusted by doping the channel. Instead, metals with different work function are utilized as the gate electrode to adjust the threshold voltage, while Dai's self-aligned structure is not compatible with this method. So, to promote the development of nanoelectronic devices and integrated circuit, it is very valuable to develop a novel self-aligned structure, which should be more stable, more flexible, and simpler.